Sdram Speed Attributes Register - Motorola MVME2400 Series Programmer's Reference Manual

System Memory Controller (SMC)

SDRAM Speed Attributes Register

Address
$FEF800D0
Bit
3
Name
Operation
Reset
The SDRAM Speed Attributes Register should be programmed based on
the SDRAM device characteristics and the Hawk's operating frequency to
ensure reliable operation.
In order for writes to this register to work properly they should be
separated from any SDRAM accesses by a refresh before the write and by
another refresh after the write. The refreshes serve two purposes: 1) they
make sure that all of the SDRAMs are idle ensuring that mode-register-set
operations for cl3 updates work properly, and 2) they make sure that no
SDRAM accesses happen during the write. A simple way to meet theses
requirments is to use the following sequence:
3-68
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1. Make sure all accesses to SDRAM are done.
2. Wait for the 32-Bit Counter
3. Perform the write/writes to this register (and other SMC registers if
desired)
4. Wait again for the 32-Bit Counter
before resuming accesses to SDRAM.
cl3 When cl3 is cleared, the SMC assumes that the SDRAM runs with
a CAS_ latency of 2. When cl3 is set, the SMC assumes that it runs
with a CAS_latency of 3.
to increment at least 100 times.
to increment at least 100 times
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