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IRV and LIRV
Operation and the
Configuration
Register
Pullup on IRQ
M68EM05C0UM/D
MOTOROLA
Freescale Semiconductor, Inc.
In single-chip mode operation:
The IRV bit defaults to 0 and internal cycles are not visible externally
until the IRV bit in the CNFGR register is set.
The LIRV bit defaults to 0 and the LIR signal is not driven out until the
LIRV bit in the CNFGR register is set.
When internal read visibility is disabled, the control signals (RD, WR,
and the chip select lines) will not be active during an internal access.
External address pins will be driven to the value of the last external
access address and the data pins will be driven to the last external
data.
In emulation:
The IRV and LIRV are defaulted to 1 and must remain a logic 1.
Writes to the CNFGR register should always leave these bits set.
The IRV jumper (W4 on the M68EM05C0) can be used to control the
control signals (LIR, RD, WR, and the chip select lines) driven out
during an internal access cycle. If the jumper is installed, the control
signals will be driven to the target. Note that even if the internal read
visibility is disabled by removing the W4 jumper, the address and data
lines of the internal cycle will still be visible to the target system in
emulation.
In single-chip mode operation:
There is no pullup on the IRQ pin. Your application must pull the IRQ
pin to V
level to prevent interrupts.
DD
In emulation:
The IRQ pin is pulled up on the module. Be aware that an application
without the IRQ pin pulled high will emulate correctly but will fail in the
application because of a floating IRQ line. The IRQ pin pulled high on
the module causes these results.
MMDS/MMEVS Configuration and Operation
For More Information On This Product,
Go to: www.freescale.com
MMDS/MMEVS Configuration and Operation
MC68HC05C0 Emulation
25
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