Data Parity Error Log Register - Motorola MVME2400 Series Programmer's Reference Manual

Writes that change these bits must be enveloped by a period of time in
which no accesses to ROM/Flash, Bank B, occur. A simple way to
provide the envelope is to perform at least two accesses to this or
another of the SMC's registers before and after the write.

Data Parity Error Log Register

Address
$FEF80068
Bit
Name
Operation
Reset
dpelog dpelog is set when a parity error occurs on the PPC60x data
bus during a PPC60x data cycle whose parity the SMC is qualified to
check. It is cleared by writing a one to it or by power-up reset.
dpe_tt0-4 dpe_tt is the value that was on the TT0-TT4 signals when
the dpelog bit was set.
DPE_DP DPE_DP is the value that was on the DP0-DP7 signals
when the dpelog bit was set.
dpe_ckall When dpe_ckall is set, the Hawk checks data parity on all
cycles in which TA_ is asserted. When dpe_ckall is cleared, the Hawk
checks data parity on cycles when TA_ is asserted only during writes
to the Hawk.
Note
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DPE_DP
READ ONLY
0 P
Note that the Hawk does not check parity during cycles in which
there is a qualified ARTRY_ at the same time as the TA_
Programming Model
GWDP
READ/WRITE
0 PL
3-59
3