Mpic Registers - Motorola MVME2400 Series Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Perspective from the PPC bus in Little-Endian mode:
2
Offset $CF8
Bit (DH)
0 1 2 3 4 5 6 7 8 9
Name CONFIG_DATA
Data 'D'
Operation R/W
Reset n/a

MPIC Registers

The following conventions are used in the Hawk register charts:
MPIC Registers
The MPIC register map is shown in the following table. The Off field is
the address offset from the base address of the MPIC registers in the PPC-
IO or PPC-MEMORY space. Note that this map does not depict linear
addressing. The PCI-SLAVE of the PHB has two decoders for generating
the MPIC select. These decoders will generate a select and acknowledge
all accesses which are in a reserved 256K byte range. If the index into that
256K block does not decode a valid MPIC register address, the logic will
return $00000000.
The registers are 8, 16, or 32 bits accessible.
2-104
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$CF9
1 1 1 1 1
0 1 2 3 4
Data 'C'
R/W
n/a
R Read Only field.
R/W Read/Write field.
S Writing a ONE to this field sets this field.
C Writing a ONE to this field clears this field.
$CFA $CFB
1 1 1 1 1 2 2 2 2 2 2
5 6 7 8 9 0 1 2 3 4 5
Data 'B' Data 'A'
R/W R/W
n/a n/a
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2 2 2 2 3 3
6 7 8 9 0 1