Error Logging; Rom/Flash Interface - Motorola MVME2400 Series Programmer's Reference Manual

Notes
1. No opportunity for error since no read of SDRAM occurs during a
four-beat write.
2. The SMC asserts its interrupt output (SMC_INT) upon detecting an
interrupt-qualified error condition. The potential sources of
SMC_INT assertion are single-bit error, multiple-bit error, and
single-bit error counter overflow. The SMC_INT signal is internally
connected to the MPIC.

Error Logging

ECC error logging is facilitated by the SMC because of its internal latches.
When an error (single- or double-bit) occurs, the SMC records the address
and syndrome bits associated with the data in error. Once the error logger
has logged an error, it does not log any more until the elog control /status
bit has been cleared by software, unless the currently logged error is
single-bit and a new, double-bit error is encountered. The logging of errors
that occur during scrub can be enabled/disabled in software. Refer to the
Error Logger Register

ROM/Flash Interface

The SMC provides the interface for two blocks of ROM/Flash. Each block
provides addressing and control for up to 64Mbytes. Note that no ECC
error checking is provided for the ROM/Flash.
The ROM/Flash interface allows each block to be individually configured
by jumpers and/or by software as follows:
1. Access for each block is controlled by three software programmable
control register bits: an overall enable, a write enable, and a reset
vector enable. The overall enable controls normal read accesses.
The write enable is used to program Flash devices. The reset vector
enable controls whether the block is also enabled at $FFF00000 -
$FFFFFFFF. The overall enable and write enable bits are always
cleared at reset. The reset vector enable bit is cleared or set at reset
depending on external jumper configuration. This allows the board
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section in this chapter.
Functional Description
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