Hardware Control-Status/Prescaler Adjust Register - Motorola MVME2400 Series Programmer's Reference Manual

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
HIER

Hardware Control-Status/Prescaler Adjust Register

The Hardware Control-Status Register (HCSR) provides hardware
specific control and status information for the PHB. The bits within the
HCSR are defined as follows:
2-74
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Priority ordering, highest to lowest
000 Group 1 -> Group 2 -> Group 3 -> Group 4
001 Group 4 -> Group 1 -> Group 2 -> Group 3
010 Group 3 -> Group 4 -> Group 1 -> Group 2
011 Group 2 -> Group 3 -> Group 4 -> Group 1
100 Reserved
101 Reserved
110 Reserved
111 Reserved
POL (Park on lock) If set, the PCI Arbiter will park the bus on the
master that successfully obtains a PCI bus lock. The PCI Arbiter keeps
the locking master parked and does not allow any non-locked masters
to obtain access of the PCI bus until the locking master releases the
lock. If this bit is cleared, the PCI Arbiter does not distinguish between
locked and non-locked cycles.
ENA (Enable) This read only bit indicates the enabled state of the PCI
Arbiter. If set, the PCI Arbiter is enabled and is acting as the system
arbiter. If cleared, the PCI Arbiter is disabled and external logic is
implementing the system arbiter. Please refer to the section titled
Hardware Configuration for more information on how this bit gets set.
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PHB