Table of Contents
Advertisement
IA-32 Intel® Architecture Optimization
Non-Sleep Clockticks
The performance monitoring counters can also be configured to count
clocks whenever the performance monitoring hardware is not
powered-down. To count "non-sleep clockticks" with a
performance-monitoring counter, do the following:
•
Select any one of the 18 counters.
•
Select any of the possible ESCRs whose events the selected counter
can count, and set its event select to anything other than no_event.
This may not seem necessary, but the counter may be disabled in
some cases if this is not done.
•
Turn threshold comparison on in the CCCR by setting the compare
bit to 1.
•
Set the threshold to 15 and the complement to 1 in the CCCR. Since
no event can ever exceed this threshold, the threshold condition is
met every cycle, and hence the counter counts every cycle. Note that
this overrides any qualification (e.g. by CPL) specified in the ESCR.
•
Enable counting in the CCCR for that counter by setting the enable
bit.
The counts produced by the Non-halted and Non-sleep metrics are
equivalent in most cases if each physical package supports one logical
processor and is not in any power-saving states. An operating system
may execute the HLT instruction and place a physical processor in a
power-saving state.
On processors that support Hyper-Threading Technology, each physical
package can support two or more logical processors. Current
implementation of Hyper-Threading Technology provides two logical
processors for each physical processor.
While both logical processors can execute two threads simultaneously,
one logical processor may be halted to allow the other logical processor
to execute without sharing execution resources between two logical
processors. "Non-halted clockticks" can be qualified to count the
number of processor clock cycles for each logical processor whenever
B-6
Advertisement
Table of Contents
