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Eventually, if the interval is large enough, the processor will be able to
enter deeper sleep and save a considerable amount of power. The
following guidelines can help applications take advantage of Intel®
Enhanced Deeper Sleep:
•
Avoid setting higher interrupt rates. Shorter periods between
interrupts may keep OSs from entering lower power states. This is
because transition to/from a deep C-state consumes power, in
addition to a latency penalty. In some cases, the overhead may
outweigh power savings.
•
Avoid polling hardware. In a ACPI C3 type state, the processor may
stop snooping and each bus activity (including DMA and bus
mastering) requires moving the processor to a lower-numbered
C-state type. The lower-numbered state type is usually C2, but may
even be C0. The situation is significantly improved in the Intel Core
Solo processor (compared to previous generations of the Pentium M
processors), but polling will likely prevent the processor from
entering into highest-numbered, processor-specific C-state.
Multi-Core Considerations
Multi-core processors deserves some special considerations when
planning power savings. The dual-core architecture in Intel Core Duo
processor provides additional potential for power savings for
multi-threaded applications.
Enhanced Intel SpeedStep
Using domain-composition, a single-threaded application can be
transformed to take advantage of multi-core processors. A
transformation into two domain threads means that each thread will
execute roughly half of the original number of instructions. Dual core
architecture enables running two threads simultaneously, each thread
using dedicated resources in the processor core. In an application that is
targeted for the mobile usages, this instruction count reduction for each
Power Optimization for Mobile Usages
®
Technology
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9-15
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