Table of Contents
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IA-32 Intel® Architecture Optimization
Table C-3
Streaming SIMD Extension 2 Double-precision Floating-point
Instructions (continued)
Instruction
COMISD xmm, xmm
CVTDQ2PD xmm, xmm
CVTPD2PI mm, xmm
CVTPD2DQ xmm, xmm
3
CVTPD2PS
xmm, xmm
CVTPI2PD xmm, mm
3
CVTPS2PD
xmm, xmm
CVTSD2SI r32, xmm
3
CVTSD2SS
xmm, xmm
3
CVTSI2SD
xmm, r32
3
CVTSS2SD
xmm, xmm
CVTTPD2PI mm, xmm
CVTTPD2DQ xmm, xmm
CVTTSD2SI r32, xmm
C-10
1
Latency
7
6
1
8
8
4+1
12
11
5
10
9
5
11
10
12
11
4+1
3
2
2+1
9
8
17
16
4
16
15
4
9
8
2
12
11
5
10
9
8
8
Throughput
2
2
1
3
3
4
3
3
3
2
2
3
2
2
2
4
4
2
3
2
2
2
4
1
2
3
1
2
2
2
3
3
3
2
2
2
2
Execution
2
Unit
FP_ADD,
FP_MISC
FP_ADD,
MMX_SHFT
FP_ADD,
MMX_SHFT,
MMX_ALU
FP_ADD,
MMX_SHFT
FP_ADD,
MMX_SHFT
FP_ADD,
MMX_SHFT,
MMX_ALU
FP_ADD,
MMX_SHFT,
MMX_ALU
FP_ADD,
FP_MISC
FP_ADD,
MMX_SHFT
FP_ADD,
MMX_SHFT,
MMX_MISC
FP_ADD,
MMX_SHFT,
MMX_ALU
FP_ADD,
MMX_SHFT
FP_ADD,
FP_MISC
continued
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