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•
Serial_Execution_Cycles, event number 3C, unit mask 02H
This event counts the bus cycles during which the core is actively
executing code (non-halted) while the other core in the physical
processor is halted.
•
L1_Pref_Req, event number 4FH, unit mask 00H
This event counts the number of times the Data Cache Unit (DCU)
requests to prefetch a data cache line from the L2 cache. Requests
can be rejected when the L2 cache is busy. Rejected requests are
re-submitted.
•
DCU_Snoop_to_Share, event number 78H, unit mask 01H
This event counts the number of times the DCU is snooped for a
cache line needed by the other core. The cache line is missing in the
L1 instruction cache or data cache of the other core; or it is set for
read-only, when the other core wants to write to it. These snoops are
done through the DCU store port. Frequent DCU snoops may
conflict with stores to the DCU, and this may increase store latency
and impact performance.
•
Bus_Not_In_Use, event number 7DH, unit mask 00H
This event counts the number of bus cycles for which the core does
not have a transaction waiting for completion on the bus.
•
Bus_Snoops, event number 77H, unit mask 00H
This event counts the number of CLEAN, HIT, or HITM responses
to external snoops detected on the bus.
In a single-processor system, CLEAN and HIT responses are not
likely to happen. In a multi-processor system this event indicates an
L2 miss in one processor that did not find the missed data on other
processors.
In a single-processor system, an HITM response indicates that an L1
miss (instruction or data) found the missed cache line in the other
core in a modified state. In a multi-processor system, this event also
indicates that an L1 miss (instruction or data) found the missed
cache line in another core in a modified state.
Using Performance Monitoring Events
B
B-59
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