Out-Of-Order Core; Table 1-3 Cache Parameters Of Pentium M, Intel; Table 1-2 Trigger Threshold And Cpuid Signatures For Ia-32 Processor Families - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization
Table 1-2 Trigger Threshold and CPUID Signatures for IA-32 Processor
Families
Trigger Thresh-
old Distance
(Bytes)
512
256
256
Data is fetched 64 bytes at a time; the instruction and data translation
lookaside buffers support 128 entries. See Table 1-3 for processor cache
parameters.
Table 1-3 Cache Parameters of Pentium M, Intel
Intel
Level Capacity
First 32 KB
Instruction 32 KB
Second 1 MB
(model 9)
Second 2 MB
(model 13)
Second 2 MB
(model 14)

Out-of-Order Core

The processor core dynamically executes µops independent of program
order. The core is designed to facilitate parallel execution by employing
many buffers, issue ports, and parallel execution units.
The out-of-order core buffers µops in a Reservation Station (RS) until
their operands are ready and resources are available. Each cycle, the
core may dispatch up to five µops through the issue ports.
1-30
Extended
Model ID
0
0
0
®
Core™ Duo Processors
Associativity
(ways)
8
8
8
8
8
Extended
Family ID Family ID
0 15
0 15
0 6
®
Core™ Solo and
Line Access
Size Latency
(bytes) (clocks)
64 3
N/A N/A
64 9
64 10
64 14
Model ID
3, 4, 6
0, 1, 2
9, 13, 14
Write Update
Policy
Writeback
N/A
Writeback
Writeback
Writeback