Table of Contents
Advertisement
IA-32 Intel® Architecture Optimization
In case the region is not mapped as
in-place in the cache and a subsequent
data being written to system memory. Explicitly mapping the region as
in this case ensures that any data read from this region will not be
WC
placed in the processor's caches. A read of this memory location by a
non-coherent I/O device would return incorrect/out-of-date results. For
a processor which solely implements approach (b), page 11, above, a
streaming store can be used in this non-coherent domain without
requiring the memory region to also be mapped as
data will be flushed to memory by the streaming store.
Streaming Store Instruction Descriptions
The
movntq/movntdq
MMX technology or Streaming SIMD Extensions register) instructions
store data from a register to memory. The instruction is implicitly
weakly-ordered, does no write-allocate, and so minimizes cache
pollution.
The
movntps
point) instruction is similar to
SIMD Extensions register to memory in 16-byte granularity. Unlike
movntq
general protection exception will occur. The instruction is implicitly
weakly-ordered, does not write-allocate, and thus minimizes cache
pollution.
6-14
CAUTION.
the line to be speculatively read into the processor
caches, that is, via the wrong path of a mispredicted
branch.
(non-temporal store of packed integer in an
(non-temporal store of packed single precision floating
, the memory address must be aligned to a 16-byte boundary or a
Failure to map the region as
, the streaming might update
WC
sfence
. It stores data from a Streaming
movntq
may allow
WC
would not result in the
, since any cached
WB
Advertisement
Table of Contents
