Intel ARCHITECTURE IA-32 Reference Manual page 498

IA-32 Intel® Architecture Optimization
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric
SSE Input
Assists
Packed SP
3
Retired
Packed DP
3
Retired
Scalar SP
3
Retired
Scalar DP
3
Retired
64-bit MMX
Instructions
3
Retired
128-bit MMX
Instructions
3
Retired
4
X87 Retired
B-44
Description
The number of
occurrences of
SSE/SSE2
floating-point
operations needing
assistance to handle
an exception
condition. The
number of
occurrences includes
speculative counts.
Non-bogus packed
single-precision
instructions retired.
Non-bogus packed
double-precision
instructions retired.
Non-bogus scalar
single-precision
instructions retired.
Non-bogus scalar
double-precision
instructions retired.
Non-bogus 64-bit
integer SIMD
instruction (MMX
instructions) retired.
Non-bogus 128-bit
integer SIMD
instructions retired.
Non-bogus x87
floating-point
instructions retired.
Event Name or Metric
Expression
SSE_input_assist
Execution_event; set
this execution tag:
Packed_SP_retired
Execution_event; set
this execution tag:
Packed_DP_retired
Execution_event; set
this execution tag:
Scalar_SP_retired
Execution_event; set
this execution tag:
Scalar_DP_retired
Execution_event; set the
following execution tag:
64_bit_MMX_retired
Execution_event; set
this execution tag:
128_bit_MMX_
retired
Execution_event; set
this execution tag:
X87_FP_retired
Event Mask Value
Required
ALL
NONBOGUS0
NONBOGUS0
NONBOGUS0
NONBOGUS0
NONBOGUS0
NONBOGUS0
NONBOGUS0
continued