Figure E-1 Pentium Ii, Pentium Iii And Pentium 4 Processors Memory Pipeline Sketch - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization
Memory access plays a pivotal role in prefetch scheduling. For more
understanding of a memory subsystem, consider Streaming SIMD
Extensions and Streaming SIMD Extensions 2 memory pipeline
depicted in Figure E-1.
Figure E-1 Pentium
Sketch
1 2 3
Assume that three cache lines are accessed per iteration and four chunks
of data are returned per iteration for each cache line. Also assume these
3 accesses are pipelined in memory subsystem. Based on these
assumptions,
T = 3 * 4 = 12 FSB cycles.
b
E-4
II , Pentium III and Pentium 4 Processors Memory Pipeline
T
l
:
L2 lookup miss latency
:
Memory page access leadoff latency
:
4
Latency for 4 chunks returned per line
1
1 2 3 4
1
1 2
T
b
3 4
1
1 2 3 4