Table 6-3 Deterministic Cache Parameters Leaf - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization
query each level of the cache hierarchy. Enumeration of each cache
level is by specifying an index value (starting form 0) in the ECX
register. The list of parameters is shown in Table 6-3.
Table 6-3 Deterministic Cache Parameters Leaf
Bit Location
EAX[4:0]
EAX[7:5]
EAX[8]
EAX[9]
EAX[13:10]
EAX[25:14]
EAX[31:26]
EBX[11:0]
EBX[21:12]
EBX[31:22]
ECX[31:0]
EDX
NOTE: CPUID leaves > 3 < 80000000 are only visible when
IA32_CR_MISC_ENABLES.BOOT_NT4 (bit 22) is clear (Default)
The deterministic cache parameter leaf provides a means to implement
software with a degree of forward compatibility with respect to
enumerating cache parameters.
The deterministic cache parameters can be used in several situations,
including:
•
Determine the size of a cache level.
•
Adapt cache blocking parameters to different sharing topology of a
cache-level across Hyper-Threading Technology, multicore and
single-core processors.
6-54
Name
Cache Type
Cache Level
Self Initializing cache level
Fully Associative cache
Reserved
Maximum number of logical processors
sharing this cache
Maximum number of cores in a package
System Coherency Line Size (L)
Physical Line partitions (P)
Ways of associativity (W)
Number of Sets (S)
Reserved
Meaning
0 = Null - No more caches
1 = Data Cache
2 = Instruction Cache
3 = Unified Cache
4-31 = Reserved
Starts at 1
1: does not need SW
initialization
1: Yes
Plus 1 encoding
Plus 1 encoding
Plus 1 encoding (Bytes)
Plus 1 encoding
Plus 1 encoding
Plus 1 encoding