Cache Management - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization
a line burst transaction. To achieve the best possible performance, it is
recommended to align data along the cache line boundary and write
them consecutively in a cache line size while using non-temporal stores.
If the consecutive writes are prohibitive due to programming
constraints, then software write-combining (
to enable line burst transaction.
You can declare small
application to enable explicit write-combining operations. Instead of
writing to non-temporal memory space immediately, the program writes
data into
program only writes a
the buffer is filled up, that is, a cache line (128 bytes for the Pentium 4
processor). Although the
performing temporary writes and reads, this ensures that the transaction
on the front-side bus causes line transaction rather than several partial
transactions. Application performance gains considerably from
implementing this technique. These SWWC buffers can be maintained
in the second-level and re-used throughout the program.

Cache Management

The streaming instructions (
manage data and minimize disturbance of temporal data held within the
processor's caches.
In addition, the Pentium 4 processor takes advantage of the Intel C ++
Compiler that supports C ++ language-level features for the Streaming
SIMD Extensions. The Streaming SIMD Extensions and MMX
technology instructions provide intrinsics that allow you to optimize
cache utilization. The examples of such Intel compiler intrinsics are
_mm_prefetch
on these intrinsics, refer to the Intel C ++ Compiler User's Guide, order
number 718195.
6-44
SWWC
buffers and combines them inside these buffers. The
SWWC
SWWC
SWWC
,
_mm_stream
SWWC
buffers (a cache line for each buffer) in your
buffer out using non-temporal stores when
method requires explicit instructions for
and
prefetch stores
, ,
_mm_load _mm_sfence
) buffers can be used
) can be used to
. For more details