Intel ARCHITECTURE IA-32 Reference Manual page 478

IA-32 Intel® Architecture Optimization
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric
Trace Cache
Misses
TC to ROM
Transfers
Speculative
TC-Built Uops
Speculative
TC-Delivered
Uops
Speculative
Microcode
Uops
B-24
Description
The number of times
that significant
delays occurred in
order to decode
instructions and build
a trace because of a
TC miss.
Twice the number of
times that the ROM
microcode is
accessed to decode
complex IA-32
instructions instead
of building|delivering
traces. (Divide the
count by 2 to get the
number of
occurrence.)
The number of
speculative uops
originating when the
TC is in build mode.
The number of
speculative uops
originating when the
TC is in deliver
mode.
The number of
speculative uops
originating from the
microcode ROM (Not
all uops of an
instruction from the
microcode ROM will
be included).
Event Name or Metric
Expression
BPU_fetch_request
tc_ms_xfer
uop_queue_writes
uop_queue_writes
uop_queue_writes
Event Mask Value
Required
TCMISS
CISC
FROM_TC_BUILD
FROM_TC_DELIVER
FROM_ROM
continued