IA-32 Intel® Architecture Optimization
Using
test
the flag register and the instruction that uses the flag register can also
help prevent partial flag register stall.
Assembly/Compiler Coding Rule 52. (ML impact, M generality) Use the
instruction instead of
test
This saves uops in execution. Use a
of the register to zero, this saves the need to encode the zero and saves
cmp
encoding space. Avoid comparing a constant to a memory operand. It is
preferable to load the memory operand and compare the constant to a register.
Often a produced value must be compared with zero, and then used in a
branch. Because most Intel architecture instructions set the condition
codes as part of their execution, the compare instruction may be
eliminated. Thus the operation can be tested directly by a
instruction. The notable exceptions are
.
test
Assembly/Compiler Coding Rule 53. (ML impact, M generality) Eliminate
unnecessary compare with zero instructions by using the appropriate
conditional jump instruction when the flags are already set by a preceding
arithmetic instruction. If necessary, use a
compare. Be certain that any code transformations made do not introduce
problems with overflow.
Floating Point/SIMD Operands
In initial Pentium 4 processor implementations, the latency of MMX or
SIMD floating point register to register moves is significant. This can
have implications for register allocation.
Moves that write a portion of a register can introduce unwanted
dependences. The
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.
2-88
instruction between the instruction that may modify part of
and
movsd reg, reg
when the result of the logical
if a register with itself instead of a
test
and
mov
instruction instead of a
test
instruction writes only the bottom
is not used.
and
jcc
. In these cases, use
lea
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