Intel ARCHITECTURE IA-32 Reference Manual page 531

Architecture optimization
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Table C-7
IA-32 x87 Floating-point Instructions (continued)
Instruction
4
FSCALE
4
FRNDINT
5
FXCH
6
FLDZ
6
FINCSTP/FDECSTP
See "Table Footnotes"
Table C-8
IA-32 General Purpose Instructions
Instruction
CPUID
ADC/SBB reg, reg
ADC/SBB reg, imm
ADD/SUB
AND/OR/XOR
BSF/BSR
BSWAP
BTC/BTR/BTS
CLI
CMP/TEST
DEC/INC
IMUL r32
IMUL imm32
IMUL
IDIV
1
IN/OUT
1
Latency
60
30
0
0
0
1
Latency
0F3n
0F2n
0x69n
8
8
8
6
1
0.5
1
0.5
16
8
1
7
8-9
1
0.5
1
1
10
14
4
14
4
15-18
4
66-80
56-70
<225
IA-32 Instruction Latency and Throughput
Throughput
7
11
1
Throughput
0F3n
0F2n
0x69n 0F2n
3
3
2
2
0.5
0.5
0.5
0.5
2
4
0.5
1
1
26
0.5
0.5
0.5
0.5
1
3
1
3
5
30
23
40
C
Execution
2
Unit
FP_MOVE
2
Execution Unit
ALU
ALU
ALU
ALU
ALU
ALU
FP_MUL
FP_MUL
continued
C-17

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