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IA-32 Intel® Architecture Optimization
4. Most commonly used x87 instructions (e.g.,
However, transcendental and some x87 instructions decode into several
μ
count the number of
5. This metric may not be supported in all models of the Pentium 4 processor family.
6. Set the following CCCR bits to make edge triggered:
7. Must program both MSR_FSB_ESCR0 and MSR_FSB_ESCR1.
8. Must program both MSR_BSU_ESCR0 and MSR_BSU_ESCR1.
Performance Metrics and Tagging Mechanisms
A number of metrics require more tags to be specified in addition to
programming a counting event; for example, the metric Split Loads
Retired requires specifying a
programming the
describes three sets of tags that are used in conjunction with three
at-retirement counting events:
execution_event
Architecture Software Developer's Manual, Volume 3B for the
description of the at-retirement events.
Tags for replay_event
Table B-2 provides a list of the tags that are used by various metrics in
Table B-1. These tags enable you to mark
execution and count the
These tags require at least two MSR's (see Table B-2, column 2 and
column 3) to tag the
tags require additional MSR (see Table B-2, column 4) to select the
event types for these tagged
column 4 are those from the Pentium 4 processor performance
monitoring events.
B-46
fmul, fadd, fdiv, fsqrt, fstp,
ops thatare actually tagged.
replay_event
. Please refer to Appendix A of the IA-32 Intel®
μ
ops so they can be detected at retirement. Some
μ
=1;
=1;
Compare
Edge
split_load_retired
to count at retirement. This section
front_end_event
μ
ops at retirement using the
μ
ops. The event names referenced in
etc.) decode into a single
ops; in these limited cases, the metrics will
=0
Threshold
tag in addition to
,
replay_event
μ
ops at earlier stage of
replay_event
μ
op.
, and
.
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