Packed Shuffle Word For 64-Bit Registers; Figure 4-8 Pshuf Instruction Example - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization

Packed Shuffle Word for 64-bit Registers

The
pshuf
immediate (
two MMX registers or one MMX register and a 64-bit memory location.
Bits 1 and 0 of the immediate value encode the source for destination
word 0 in MMX register (
Bits
1 - 0
3 - 2
5 - 4
7 - 6
Bits 7 and 6 encode for word 3 in MMX register (
the 2-bit encoding represents which source word is used, for example,
binary encoding of 10 indicates that source word 2 in MMX
register/memory (
Example 4-11.

Figure 4-8 pshuf Instruction Example

4-18
instruction (see Figure 4-8, Example 4-11) uses the
) operand to select between the four words in either
imm8
[15-0]
Word
0
1
2
3
/
mm mem[47-32]
63
X4
63
X1
), and so on as shown in the table:
) is used, see Figure 4-8 and
M M/m 64
X3 X2 X1
MM
X2 X3 X4
OM15166
). Similarly,
[63-48]
0
0