Example 6-7 Data Access Of A 3D Geometry Engine Without Strip-Mining - Intel ARCHITECTURE IA-32 Reference Manual

In scenario to the right, in Figure 6-7, keeping the data in one way of the
second-level cache does not improve cache locality. Therefore, use
prefetcht0
memory references in passes 1 and 2, and keeps a copy of the data in
second-level cache, which reduces memory traffic and latencies for
passes 3 and 4. To further reduce the latency, it might be worth
considering extra
references in passes 3 and 4.
In Example 6-7, consider the data access patterns of a 3D geometry
engine first without strip-mining and then incorporating strip-mining.
Note that 4-wide SIMD instructions of Pentium III processor can
process 4 vertices per every iteration.
Example 6-7 Data Access of a 3D Geometry Engine without Strip-mining
while (nvtx < MAX_NUM_VTX) {
prefetchnta vertex
prefetchnta vertex
prefetchnta vertex
prefetchnta vertex
TRANSFORMATION code
nvtx+=4
}
while (nvtx < MAX_NUM_VTX) {
prefetchnta vertex
prefetchnta vertex
prefetchnta vertex
prefetchnta vertex
compute the light vectors
LOCAL LIGHTING code
nvtx+=4
}
to prefetch the data. This amortizes the latency of the
prefetchnta
data // v =[x,y,z,nx,ny,nz,tu,tv]
i
data
i+1
data
i+2
data
i+3
// use only x,y,z,tu,tv of a vertex
data // v =[x,y,z,nx,ny,nz,tu,tv]
i
// x,y,z fetched again
data
i+1
data
i+2
data
i+3
// use only x,y,z
// use only nx,ny,nz
Optimizing Cache Usage
instructions prior to the memory
6
6-37