Supplemental Techniques For Avoiding Cache Line Splits; Example 4-28 An Example Of Video Processing With Cache Line Splits - Intel ARCHITECTURE IA-32 Reference Manual

4
Optimizing for SIMD Integer Applications
These transformations, in general, increase the number of instructions
required to perform the desired operation. For Pentium II, Pentium III,
and Pentium 4 processors, the benefit of avoiding forwarding problems
outweighs the performance penalty due to the increased number of
instructions, making the transformations worthwhile.

Supplemental Techniques for Avoiding Cache Line Splits

Some video processing applications sometimes cannot avoid loading
data from memory address that are aligned to 16 byte boundary. An
example of this situation is when each line in a video frame is averaged
by shifting horizontally half a pixel. Example 4-28 shows a common
operation in video processing that loads data from memory address not
aligned to 16 byte boundary. As video processing traverses each line in
the video frame, it will experience at least a cache line split for each
64 bytes loaded from memory.

Example 4-28 An Example of Video Processing with Cache Line Splits

// Average half-pels horizonally (on // the "x" axis),
// from one reference frame only.
nextLinesLoop:
movdqu xmm0, XMMWORD PTR [edx] // may not be 16B aligned
movdqu xmm0, XMMWORD PTR [edx+1]
movdqu xmm1, XMMWORD PTR [edx+eax]
movdqu xmm1, XMMWORD PTR [edx+eax+1]
pavgbxmm0, xmm1
pavgbxmm2, xmm3
movdqaXMMWORD PTR [ecx], xmm0
movdqaXMMWORD PTR [ecx+eax], xmm2
// (repeat ...)
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