Intel ARCHITECTURE IA-32 Reference Manual page 529

Architecture optimization
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Table C-6
MMX Technology 64-bit Instructions (continued)
Instruction
PCMPGTB/PCMPGTD/
PCMPGTW mm, mm
3
PMADDWD
mm, mm
3
PMULHW/PMULLW
mm, mm
POR mm, mm
PSLLQ/PSLLW/
PSLLD mm, mm/imm8
PSRAW/PSRAD mm,
mm/imm8
PSRLQ/PSRLW/PSRLD
mm, mm/imm8
PSUBB/PSUBW/PSUBD
mm, mm
PSUBSB/PSUBSW/PSU
BUSB/PSUBUSW mm,
mm
PUNPCKHBW/PUNPCK
HWD/PUNPCKHDQ
mm, mm
PUNPCKLBW/PUNPCK
LWD/PUNPCKLDQ mm,
mm
PXOR mm, mm
1
EMMS
See "Table Footnotes"
IA-32 Instruction Latency and Throughput
1
Latency
2
2
9
8
9
8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
12
Throughput
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
12
C
2
Execution Unit
MMX_ALU
FP_MUL
FP_MUL
MMX_ALU
MMX_SHFT
MMX_SHFT
MMX_SHFT
MMX_ALU
MMX_ALU
MMX_SHFT
MMX_SHFT
MMX_ALU
C-15

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