Table B-4 Metrics That Utilize The Execution Tagging Mechanism - Intel ARCHITECTURE IA-32 Reference Manual

Architecture optimization
Table of Contents

Advertisement

Table B-4
Metrics That Utilize the Execution Tagging Mechanism
Execution Metric Tags
Packed_SP_retired
Scalar_SP_retired
Scalar_DP_retired
128_bit_MMX_retired
64_bit_MMX_retired
X87_FP_retired
Upstream ESCR
Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of packed_SP_uop.
Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of scalar_SP_uop.
Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of scalar_DP_uop.
Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of 128_bit_MMX_uop.
Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of 64_bit_MMX_uop.
Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of x87_FP_uop.
Using Performance Monitoring Events
See Event Mask
Tag Value in
Parameter for
Upstream
Execution_
ESCR
event
1
NBOGUS0
1
NBOGUS0
1
NBOGUS0
1
NBOGUS0
1
NBOGUS0
1
NBOGUS0
B
B-49

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the ARCHITECTURE IA-32 and is the answer not in the manual?

Questions and answers

Table of Contents