Figure 6-8 Single-Pass Vs. Multi-Pass 3D Geometry Engines - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization
selected to ensure that the batch stays within the processor caches
through all passes. An intermediate cached buffer is used to pass the
batch of vertices from one stage or pass to the next one.
Single-pass execution can be better suited to applications which limit
the number of features that may be used at a given time. A single-pass
approach can reduce the amount of data copying that can occur with a
multi-pass engine, see Figure 6-8.

Figure 6-8 Single-Pass Vs. Multi-Pass 3D Geometry Engines

strip list
80 vis
60 invis
40 vis
80 vis
40 vis
Vertex
processing
(inner loop)
6-42
Culling
Transform
Lighting
Single-Pass
Outer loop is
processing
strips
Multi-Pass
Culling
Transform
Lighting