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IA-32 Intel® Architecture Optimization
An additional positive effect of continuously operating at a lower
frequency is that frequent changes in power draw (from low to high in
our case) and battery current eventually harm the battery. They
accelerate its deterioration.
When the lowest possible operating point (highest P-state) is reached,
there is no need for dividing computations. Instead, use longer idle
periods to allow the processor to enter a deeper low power mode.
Enabling Intel
In typical mobile computing usages, the processor is idle most of the
time. Conserving battery life must address reducing static power
consumption.
Typical OS power management policy periodically evaluates
opportunities to reduce static power consumption by moving to
lower-power C-states. Generally, the longer a processor stays idle, OS
power management policy directs the processor into deeper low-power
C-states.
After an application reaches the lowest possible P-state, it should
consolidate computations in larger chunks to enable the processor to
enter deeper C-States between computations. This technique utilizes the
fact that the decision to change frequency is made based on a larger
window of time than the period to decide to enter deep sleep. If the
processor is to enter a processor-specific C4 state to take advantage of
aggressive static power reduction features, the decision should be based
on:
•
Whether the QOS can be maintained in spite of the fact that the
processor will be in a low-power, long-exit-latency state for a long
period.
•
Whether the interval in which the processor stays in C4 is long
enough to amortize the longer exit latency of this low-power C state.
9-14
®
Enhanced Deeper Sleep
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