Intel ARCHITECTURE IA-32 Reference Manual page 482

IA-32 Intel® Architecture Optimization
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric
2nd-Level
Cache Reads
Hit Shared
2nd-Level
Cache Reads
Hit Modified
2nd-Level
Cache Reads
Hit Exclusive
3rd-Level
Cache Reads
Hit Shared
B-28
Description
The number of
2nd-level cache read
references (loads
and RFOs) that hit
the cache line in
shared state. Beware
of granularity
differences.
The number of
2nd-level cache read
references (loads
and RFOs) that hit
the cache line in
modified state.
Beware of granularity
differences.
The number of
2nd-level cache read
references (loads
and RFOs) that hit
the cache line in
exclusive state.
Beware of granularity
differences.
The number of
3rd-level cache read
references (loads
and RFOs) that hit
the cache line in
shared state. Beware
of granularity
differences.
Event Name or Metric
Expression
BSQ_cache_reference
BSQ_cache_reference
BSQ_cache_reference
BSQ_cache_reference
Event Mask Value
Required
RD_2ndL_HITS
RD_2ndL_HITM
RD_2ndL_HITE
RD_3rdL_HITS
continued