Caches; Figure 1-4 Execution Units And Ports In The Out-Of-Order Core - Intel ARCHITECTURE IA-32 Reference Manual

Figure 1-4 Execution Units and Ports in the Out-Of-Order Core

Port 0
ALU 0
Double
Move
Speed
ADD/SUB FP Move
Logic FP Store Data
Store Data FXCH
Branches
Note:
FP_ADD refers to x87 FP, and SIMD FP add and subtract operations
FP_MUL refers to x87 FP, and SIMD FP m ultiply operations
FP_DIV refers to x87 FP, and SIMD FP divide and square root operations
MMX_ALU refers to SIMD integer arithm etic and logic operations
MMX_SHFT handles Shift, Rotate, Shuffle, Pack and Unpack operations
MMX_MISC handles SIMD reciprocal and som e integer operations

Caches

The Intel NetBurst microarchitecture supports up to three levels of
on-chip cache. At least two levels of on-chip cache are implemented in
processors based on the Intel NetBurst microarchitecture. The Intel
Xeon processor MP and selected Pentium and Intel Xeon processors
may also contain a third-level cache.
The first level cache (nearest to the execution core) contains separate
caches for instructions and data. These include the first-level data cache
and the trace cache (an advanced first-level instruction cache). All other
caches are shared between instructions and data.
ALU 1
FP
Double
Speed
ADD/SUB
IA-32 Intel® Architecture Processor Family Overview
Port 1
Integer
FP
Operation
Execute
Norm al
Speed
Shift/Rotate FP_ADD
FP_MUL
FP_DIV
FP_MISC
MMX_SHFT
MMX_ALU
MMX_MISC
Port 3
Port 2
Mem ory Mem ory
Load Store
All Loads Store
Prefetch
Address
OM15151
1-19