Intel ARCHITECTURE IA-32 Reference Manual page 12

Architecture optimization
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Sign Extension to Full 64-Bits........................................................................................... 8-3
Alternate Coding Rules for 64-Bit Mode.................................................................................. 8-4
Using Software Prefetch................................................................................................... 8-6
Overview ................................................................................................................................. 9-1
Mobile Usage Scenarios ......................................................................................................... 9-2
ACPI C-States ......................................................................................................................... 9-4
Processor-Specific C4 and Deep C4 States ..................................................................... 9-6
Guidelines for Extending Battery Life...................................................................................... 9-7
Adjust Performance to Meet Quality of Features ............................................................. 9-8
Reducing Amount of Work................................................................................................ 9-9
Platform-Level Optimizations.......................................................................................... 9-10
Handling Sleep State Transitions ................................................................................... 9-11
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Multi-Core Considerations .............................................................................................. 9-15
Thread Migration Considerations.............................................................................. 9-16
Multi-core Considerations for C-States ..................................................................... 9-17
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Code Optimization Options ............................................................................................. A-3
Targeting a Processor (-Gn) ...................................................................................... A-3
Vectorizer Switch Options ............................................................................................... A-5
Loop Unrolling............................................................................................................ A-5
Multithreading with OpenMP* .................................................................................... A-6
Inline Expansion of Library Functions (-Oi, -Oi-) ............................................................. A-6
Floating-point Arithmetic Precision (-Op, -Op-, -Qprec, -Qprec_div, -Qpc,
-Qlong_double)............................................................................................................ A-6
Rounding Control Option (-Qrcd) .................................................................................... A-6
Interprocedural and Profile-Guided Optimizations .......................................................... A-7
Interprocedural Optimization (IPO) ............................................................................ A-7
Profile-Guided Optimization (PGO) ........................................................................... A-7
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Sampling ......................................................................................................................... A-9
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Enhanced Deeper Sleep ....................................................................... 9-14
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Technology .................................................................. 9-15
Technology ............................................................. 9-12

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