Partial Memory Accesses; Example 4-24 A Large Load After A Series Of Small Stores (Penalty); Example 4-25 Accessing Data Without Delay - Intel ARCHITECTURE IA-32 Reference Manual

Partial Memory Accesses

Consider a case with large load after a series of small stores to the same
area of memory (beginning at memory address
stall in this case as shown in Example 4-24.

Example 4-24 A Large Load after a Series of Small Stores (Penalty)

mov mem, eax
mov mem + 4, ebx
:
:
movq mm0, mem
The
movq
all the data it requires. This stall can also occur with other data types
(for example, when bytes or words are stored and then words or
doublewords are read from the same area of memory). When you
change the code sequence as shown in Example 4-25, the processor can
access the data without delay.

Example 4-25 Accessing Data without Delay

movd
movd
psllq
por
movq
movq
; store dword to address "mem"
; store dword to address "mem + 4"
; load qword at address "mem", stalls
must wait for the stores to write memory before it can access
mm1, ebx ; build data into a qword first
; before storing it to memory
mm2, eax
mm1, 32
mm1, mm2
mem, mm1 ; store SIMD variable to "mem" as
; a qword
:
:
mm0, mem ; load qword SIMD "mem", no stall
Optimizing for SIMD Integer Applications
). The large load will
mem
4
4-35