Figure 6-5 Memory Access Latency And Execution With Prefetch - Intel ARCHITECTURE IA-32 Reference Manual

Figure 6-5 Memory Access Latency and Execution With Prefetch

350
300
250
200
150
100
50
0
48
350
300
250
200
150
100
50
54
One load and one store stream
16_por 32_por 64_por
108 144 192
Computations per loop
2 Load streams, 1 store stream
16
% Bus Utilization
108 144 192
Computations per loop
128_por None_por
% Bus Utilization
240 336
32 64 128 none
240 336
Optimizing Cache Usage
100.00%
90.00%
80.00%
70.00%
60.00%
50.00%
40.00%
30.00%
20.00%
10.00%
0.00%
408
100.00%
90.00%
80.00%
70.00%
60.00%
50.00%
40.00%
30.00%
20.00%
10.00%
0.00%
390
6
6-31