Optimize Branch Predictability; Optimize Memory Access - Intel ARCHITECTURE IA-32 Reference Manual

Optimize Branch Predictability

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Improve branch predictability and optimize instruction prefetching
by arranging code to be consistent with the static branch prediction
assumption: backward taken and forward not taken.
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Avoid mixing near calls, far calls and returns.
•
Avoid implementing a call by pushing the return address and
jumping to the target. The hardware can pair up call and return
instructions to enhance predictability.
•
Use the
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Inline functions according to coding recommendations.
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Whenever possible, eliminate branches.
•
Avoid indirect calls.

Optimize Memory Access

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Observe store-forwarding constraints.
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Ensure proper data alignment to prevent data split across cache line.
boundary. This includes stack and passing parameters.
•
Avoid mixing code and data (self-modifying code).
•
Choose data types carefully (see next bullet below) and avoid type
casting.
•
Employ data structure layout optimization to ensure efficient use of
64-byte cache line size.
•
Favor parallel data access to mask latency over data accesses with
dependency that expose latency.
•
For cache-miss data traffic, favor smaller cache-miss strides to
avoid frequent DTLB misses.
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Use prefetching appropriately.
•
Use the following techniques to enhance locality: blocking,
hardware-friendly tiling, loop interchange, loop skewing.
instruction in spin-wait loops.
pause
General Optimization Guidelines
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