Intel ARCHITECTURE IA-32 Reference Manual page 242

IA-32 Intel® Architecture Optimization
Example 4-15 Generating Constants (continued)
pxor MM0, MM0
pcmpeq MM1, MM1
psubb MM0, MM1 [psubw
pcmpeq MM1, MM1
psrlw MM1, 16-n(psrld
pcmpeq MM1, MM1
psllw MM1, n (pslld MM1, n)
4-22
MM0, MM1] (psubd
; three instructions above generate
; the constant 1 in every
; packed-byte [or packed-word]
; (or packed-dword) field
MM1, 32-n)
; two instructions above generate
; the signed constant 2
; packed-word (or packed-dword) field
; two instructions above generate
; the signed constant -2n in every
; packed-word (or packed-dword) field
Because the SIMD integer instruction sets do
NOTE.
not support shift instructions for bytes,
are relevant only for packed words and packed
doublewords.
MM0, MM1)
n
–1 in every
n
2 –1
and
n
-2