Using 16-Byte Streaming Stores And Hardware Prefetch; Example 6-12 Memory Copy Using Hardware Prefetch And Bus Segmentation - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization
The instruction,
table entry for array, and
This is essentially a prefetch itself, as a cache line is filled from that
memory location with this instruction. Hence, the prefetching starts
from
kk+4
This example assumes that the destination of the copy is not temporally
adjacent to the code. If the copied data is destined to be reused in the
near future, then the streaming store instructions should be replaced
with regular 128 bit stores(
implementation of streaming stores on Pentium 4 processor writes data
directly to memory, maintaining cache coherency.

Using 16-byte Streaming Stores and Hardware Prefetch

An alternate technique for optimizing a large region memory copy is to
take advantage of hardware prefetcher, 16-byte streaming stores, and
apply a segmented approach to separate bus.read and write transactions
(see "Minimizing Bus Latency" in Chapter 2). This technique employs
two stages. In the first stage, a block of data is read from memory to the
cache sub-system. In the second stage, cached data are written to their
destination using streaming stores.

Example 6-12 Memory Copy Using Hardware Prefetch and Bus Segmentation

void block_prefetch(void *dst,void *src)
{ _asm {
main_loop:
}
6-50
temp = a[kk+CACHESIZE]
a
in this loop.
mov edi,dst
mov esi,src
mov edx,SIZE
align 16
xor ecx,ecx
align 16
is entered in the TLB prior to prefetching.
. This is required because the
_mm_store_ps)
, is used to ensure the page