Compute Bound (Case:tc >= T L + T B; Compute Bound (Case: Tl + Tb > Tc > Tb; Figure E-4 Another Compute Bound Execution Pipeline - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization
The following formula shows the relationship among the parameters:
It can be seen from this relationship that the iteration latency is equal to
the computation latency, which means the memory accesses are
executed in background and their latencies are completely hidden.
Compute Bound (Case: T
Now consider the next case by first examining Figure E-4.

Figure E-4 Another Compute Bound Execution Pipeline

Front-Side Bus
T
i
l
i+1
Execution pipeline
T
i
c
i+1
E-8
+ T > T
l b
Execution cycles
T
b
T T
l
i+2
δ
f
T
c
T
i+2
> T )
c b
b
T T
l b
T
i+3
δ
f
c
T
i+3
c
T
l b
δ
f
T
i+4
c