Intel ARCHITECTURE IA-32 Reference Manual page 479

Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Memory Metrics
Page Walk The number of page
DTLB All walk requests due to
Misses DTLB misses from
either load or store.
st
1 -Level Cache The number of
retired μops that
Load Misses
Retired experienced
st
1
misses. This stat is
often used in a
per-instruction ratio.
nd
2 -Level The number of
retired load μops that
Cache Load
Misses Retired experienced
nd
2
misses. This stat is
known to undercount
when loads are
spaced apart.
DTLB Load The number of
retired load μops that
Misses Retired
experienced DTLB
misses.
DTLB Store The number of
retired store μops
Misses Retired
that experienced
DTLB misses.
DTLB Load and The number of
retired load or μops
Store Misses
Retired that experienced
DTLB misses.
Event Name or Metric
Expression
page_walk_type
Replay_event; set the
following replay tag:
1stL_cache_load
-Level cache load
_miss_retired
Replay_event; set the
following replay tag:
2ndL_cache_load_
-Level cache
miss_retired
Replay_event; set the
following replay tag:
DTLB_load_miss_
retired
Replay_event; set the
following replay tag:
DTLB_store_miss_
retired
Replay_event; set the
following replay tag:
DTLB_all_miss_
retired
Using Performance Monitoring Events
Event Mask Value
Required
DTMISS
NBOGUS
NBOGUS
NBOGUS
NBOGUS
NBOGUS
B
continued
B-25