Using Performance Metrics With Hyper-Threading Technology; Table B-5 New Metrics For Pentium 4 Processor (Family 15, Model 3 - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization
Table B-5 New Metrics for Pentium 4 Processor (Family 15, Model 3)
Metric
Instructions
Completed
Speculative
Instructions
Completed
Using Performance Metrics with Hyper-Threading
Technology
On Intel Xeon processors that support Hyper-Threading Technology, the
performance metrics listed in Table B-1 may be qualified to associate
the counts with a specific logical processor, provided the relevant
performance monitoring events supports qualification by logical
processor. Within the subset of those performance metrics that support
qualification by logical processors, some of them can be programmed
with parallel ESCRs and CCCRs to collect separate counts for each
logical processor simultaneously. For some metrics, qualification by
logical processor is supported but there is not sufficient number of
MSRs for simultaneous counting of the same metric on both logical
processors. In both cases, it is also possible to program the relevant
ESCR for a performance metric that supports qualification by logical
processor to produce counts that are, typically, the sum of contributions
from both logical processors.
A number of performance metrics are based on performance monitoring
events that do not support qualification by logical processor. Any
attempts to program the relevant ESCRs to qualify counts by logical
processor will not produce different results. The results obtained in this
manner should not be summed together.
B-50
Descriptions
Non-bogus IA-32
instructions
completed and
retired.
Number of IA-32
instructions decoded
and executed
speculatively.
Event Name or
Metric Expression
instr_completed
instr_completed
Event Mask value
required
NBOGUS
BOGUS