Table of Contents
Advertisement
IA-32 Intel® Architecture Optimization
Table C-8
IA-32 General Purpose Instructions (continued)
Instruction
7
Jcc
LOOP
MOV
MOVSB/MOVSW
MOVZB/MOVZW
NEG/NOT/NOP
POP r32
PUSH
8
RCL/RCR reg, 1
ROL/ROR
RET
SAHF
SAL/SAR/SHL/SHR
SCAS
SETcc
STI
STOSB
XCHG
CALL
MUL
DIV
See "Table Footnotes"
C-18
1
Latency
Not
Appli-
cable
8
1
0.5
1
0.5
1
0.5
1
0.5
1.5
1.5
6
4
1
4
8
1
0.5
1
4
4
5
5
1.5
1.5
5
10
14-18
66-80
56-70
Throughput
0.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1
1
1
1
0.5
1
1
0.5
0.5
1
0.5
1
1.5
1.5
36
2
1
1
1
1
5
30
23
2
Execution Unit
ALU
ALU
ALU
ALU
ALU
ALU
MEM_LOAD,
ALU
MEM_STORE,
ALU
MEM_LOAD,
ALU
ALU
ALU,MEM_
LOAD
ALU
ALU,MEM_
STORE
ALU
ALU,MEM_
STORE
Advertisement
Table of Contents
