Intel ARCHITECTURE IA-32 Reference Manual page 508

IA-32 Intel® Architecture Optimization
Table B-6 Metrics That Support Qualification by Logical Processor and
Parallel Counting (continued)
Bus Metrics
B-54
Bus Accesses from the Processor
Non-prefetch Bus Accesses from the Processor
Reads from the Processor
Writes from the Processor
Reads Non-prefetch from the Processor
All WC from the Processor
All UC from the Processor
Bus Accesses from All Agents
Bus Accesses Underway from the processor
Bus Reads Underway from the processor
Non-prefetch Reads Underway from the processor
All UC Underway from the processor
All WC Underway from the processor
Bus Writes Underway from the processor
Bus Accesses Underway from All Agents
Write WC Full (BSQ)
Write WC Partial (BSQ)
Writes WB Full (BSQ)
Reads Non-prefetch Full (BSQ)
Reads Invalidate Full- RFO (BSQ)
UC Reads Chunk (BSQ)
UC Reads Chunk Split (BSQ)
UC Write Partial (BSQ)
IO Reads Chunk (BSQ)
IO Writes Chunk (BSQ)
WB Writes Full Underway (BSQ)
UC Reads Chunk Underway (BSQ)
Write WC Partial Underway(BSQ)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
continued