Intel ARCHITECTURE IA-32 Reference Manual page 179

2
General Optimization Guidelines
Assembly/Compiler Coding Rule 56. (M impact, ML generality) For
arithmetic or logical operations that have their source operand in memory
and the destination operand is in a register, attempt a strategy that
initially loads the memory operand to a register followed by a register to
register ALU operation. Next, attempt to remove redundant loads by
identifying loads from the same memory location. Finally, combine the
remaining loads with their corresponding ALU operations. 2-81
Assembly/Compiler Coding Rule 57. (ML impact, M generality) Give
preference to adding a register to memory (memory is the destination)
instead of adding memory to a register. Also, give preference to adding a
register to memory over loading the memory, adding two registers and
storing the result. 2-82
Assembly/Compiler Coding Rule 58. (M impact, M generality) When
an address of a store is unknown, subsequent loads cannot be scheduled to
execute out of order ahead of the store, limiting the out of order execution
of the processor. When an address of a store is computed by a potentially
long latency operation (such as a load that might miss the data cache)
attempt to reorder subsequent loads ahead of the store. 2-82
Assembly/Compiler Coding Rule 59. (M impact, MH generality)
Calculate store addresses as early as possible to avoid having stores block
loads. 2-82
Assembly/Compiler Coding Rule 60. (H impact, MH generality) For
small loops, placing loop invariants in memory is better than spilling
loop-carried dependencies. 2-83
Assembly/Compiler Coding Rule 61. (M impact, M generality) Avoid
putting explicit references to ESP in a sequence of stack operations ( ,
POP
, , ). 2-84
PUSH CALL RET
2-107