No Preloading Or Prefetch; Figure E-2 Execution Pipeline, No Preloading Or Prefetch - Intel ARCHITECTURE IA-32 Reference Manual

IA-32 Intel® Architecture Optimization

No Preloading or Prefetch

The traditional programming approach does not perform data
preloading or prefetch. It is sequential in nature and will experience
stalls because the memory is unable to provide the data immediately
when the execution pipeline requires it. Examine Figure E-2.

Figure E-2 Execution Pipeline, No Preloading or Prefetch

Execution
T - T
Δ
c
pipeline
Front-Side
Bus
As you can see from Figure E-2, the execution pipeline is stalled while
waiting for data to be returned from memory. On the other hand, the
front side bus is idle during the computation portion of the loop. The
memory access latencies could be hidden behind execution if data could
be fetched earlier during the bus idle time.
Further analyzing Figure E-2,
•
assume execution cannot continue till last chunk returned and
δ
•
f
indicates flow data dependency that stalls the execution pipelines
With these two things in mind the iteration latency (il) is computed as
follows:
≅
il T +
c
E-6
Execution units idle
issue loads
T
l
th
i iteration
T + T
b
l
Execution cycles
T
T - T
Δ
Δ
c
δ issue loads
f
FSB idle
T
b
Execution units idle
T T
l
th
(i+1) iteration
T
Δ
δ
f
b