Intel ARCHITECTURE IA-32 Reference Manual page 26

Architecture optimization
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IA-32 Intel® Architecture Optimization
Chapter 7: Multiprocessor and Hyper-Threading Technology.
Describes guidelines and techniques for optimizing multithreaded
applications to achieve optimal performance scaling. Use these when
targeting multiprocessor (MP) systems or MP systems using IA-32
processors that support Hyper-Threading Technology.
Chapter 8: 64-Bit Mode Coding Guidelines. This chapter describes a
set of additional coding guidelines for application software written to
run in 64-bit mode.
Chapter 9: Power Optimization for Mobile Usages. This chapter
provides background on power saving techniques in mobile processors
and makes recommendations that developers can leverage to provide
longer battery life.
Appendix A: Application Performance Tools. Introduces tools for
analyzing and enhancing application performance without having to
write assembly code.
Appendix B: Intel Pentium 4 Processor Performance Metrics.
Provides information that can be gathered using Pentium 4 processor's
performance monitoring events. These performance metrics can help
programmers determine how effectively an application is using the
features of the Intel NetBurst microarchitecture.
Appendix C: IA-32 Instruction Latency and Throughput. Provides
latency and throughput data for the IA-32 instructions. Instruction
timing data specific to the Pentium 4 and Pentium M processors are
provided.
Appendix D: Stack Alignment. Describes stack alignment conventions
and techniques to optimize performance of accessing stack-based data.
Appendix E: The Mathematics of Prefetch Scheduling Distance.
Discusses the optimum spacing to insert
instructions and
prefetch
presents a mathematical model for determining the prefetch scheduling
distance (PSD) for your application.
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