Intel ARCHITECTURE IA-32 Reference Manual page 480

IA-32 Intel® Architecture Optimization
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric
64K Aliasing
1
Conflicts
Split Load
Replays
Split Loads
Retired
Split Store
Replays
Split Stores
Retired
B-26
Description
The number of 64K
aliasing conflicts. A
memory reference
causing 64K aliasing
conflict can be
counted more than
once in this stat. The
performance penalty
resulted from
64K-aliasing conflict
can vary from being
unnoticeable to
considerable. Some
implementations of
the Pentium 4
processor family can
incur significant
penalties for loads
that alias to
preceding stores.
The number of load
references to data
that spanned two
cache lines.
The number of
retired load μops that
spanned two cache
lines.
The number of store
references that
spans across cache
line boundary.
The number of
retired store μops
that spanned two
cache lines.
Event Name or Metric
Expression
Memory_cancel
Memory_complete
Replay_event; set the
following replay tag:
Split_load_retired.
Memory_complete
Replay_event; set the
following replay tag:
Split_store_retired
.
Event Mask Value
Required
64K_CONF
LSC
NBOGUS
SSC
NBOGUS
continued