Summary Of Simd Technologies; Mmx™ Technology; Streaming Simd Extensions - Intel ARCHITECTURE IA-32 Reference Manual

SSE and SSE2 instructions also introduced cacheability and memory
ordering instructions that can improve cache usage and application
performance.
For more on SSE, SSE2, SSE3 and MMX technologies, see:
IA-32 Intel® Architecture Software Developer's Manual, Volume 1:
Chapter 9, "Programming with Intel® MMX™ Technology";
Chapter 10, "Programming with Streaming SIMD Extensions
(SSE)"; Chapter 11, "Programming with Streaming SIMD
Extensions 2 (SSE3)"; Chapter 12, "Programming with Streaming
SIMD Extensions 3 (SSE3)"

Summary of SIMD Technologies

MMX™ Technology
MMX Technology introduced:
•
64-bit MMX registers
•
support for SIMD operations on packed byte, word, and doubleword
integers
MMX instructions are useful for multimedia and communications
software.

Streaming SIMD Extensions

Streaming SIMD extensions introduced:
•
128-bit XMM registers
•
128-bit data type with four packed single-precision floating-point
operands
•
data prefetch instructions
•
non-temporal store instructions and other cacheability and memory
ordering instructions
•
extra 64-bit SIMD integer support
IA-32 Intel® Architecture Processor Family Overview
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