Key Practices Of System Bus Optimization; Key Practices Of Memory Optimization - Intel ARCHITECTURE IA-32 Reference Manual

•
Place each synchronization variable alone, separated by 128 bytes
or in a separate cache line.
See "Thread Synchronization" for more details.

Key Practices of System Bus Optimization

Managing bus traffic can significantly impact the overall performance
of multithreaded software and MP systems. Key practices of system bus
optimization for achieving high data throughput and quick response are:
•
Improve data and code locality to conserve bus command
bandwidth.
•
Avoid excessive use of software prefetch instructions and allow the
automatic hardware prefetcher to work. Excessive use of software
prefetches can significantly and unnecessarily increase bus
utilization if used inappropriately.
•
Consider using overlapping multiple back-to-back memory reads to
improve effective cache miss latencies.
•
Use full write transactions to achieve higher data throughput.
See "System Bus Optimization" for more details.

Key Practices of Memory Optimization

Key practices for optimizing memory operations are summarized
below:
•
Use cache blocking to improve locality of data access. Target one
quarter to one half of cache size when targeting IA-32 processors
supporting Hyper-Threading Technology.
•
Minimize the sharing of data between threads that execute on
different physical processors sharing a common bus.
•
Minimize data access patterns that are offset by multiples of 64 KB
in each thread.
Multi-Core and Hyper-Threading Technology
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