Packed Shuffle Word For 128-Bit Registers; Example 4-12 Broadcast Using 2 Instructions; Example 4-11 Pshuf Instruction Code - Intel ARCHITECTURE IA-32 Reference Manual

Example 4-11 pshuf Instruction Code

; Input:
;
; Output:
;
movq
pshufw

Packed Shuffle Word for 128-bit Registers

The
pshuflw
word field within the low/high 64 bits to any result word field in the
low/high 64 bits, using an 8-bit immediate operand; the other high/low
64 bits are passed through from the source operand.
The
pshufd
within the 128-bit source to any double-word field in the 128-bit result,
using an 8-bit immediate operand.
No more than 3 instructions, using
required to implement some common data shuffling operations.
Broadcast, Swap, and Reverse are illustrated in Example 4-12,
Example 4-13, and Example 4-14, respectively.

Example 4-12 Broadcast Using 2 Instructions

/* Goal:
/* Instruction Result */
PSHUFHW (3,2,1,1)| 7| 6| 5| 5| 3| 2| 1| 0|
PSHUFD (2,2,2,2)| 5| 5| 5| 5| 5| 5| 5| 5|
edi source value
MM1 MM register containing re-arranged words
mm0, [edi]
mm1, mm0, 0x1b
/ instruction performs a full shuffle of any source
pshufhw
instruction performs a full shuffle of any double-word field
Broadcast the value from word 5 to all words */
| 7| 6| 5| 4| 3| 2| 1| 0|
Optimizing for SIMD Integer Applications
/ /
pshuflw pshufhw pshufd
4
, are
4-19