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M68000
CORE
MICROCODED
COMMUNICATIONS
CONTROLLER
(RISC)
The use of a unique arbitration scheme and synchronous transfers between the micropro-
cessor and dual-port RAM gives zero wait-state operation to the M68000 microprocessor
core. The dual-port RAM can be accessed by the CP main controller (RISC) once every
clock cycle for either read or write operations. When the M68000 core accesses the dual-
port RAM, each access is pipelined along with the CP accesses so that data is read or writ-
ten without conflict. The net effect is the loss of a single memory access by the CP main
controller per M68000 core access.
The buffer memory structure of the MC68302 can be configured to closely match I/O chan-
nel requirements by careful selection of buffer size and buffer linking. The interrupt structure
is also programmable so that the on-chip M68000 processor can be off-loaded from the pe-
ripheral bit-handling functions to perform higher layer application software or protocol pro-
cessing.
1.4 NMSI COMMUNICATIONS-ORIENTED ENVIRONMENT
When the interface to equipment or proprietary networks requires the use of standard con-
trol and data signals, the MC68302 can be programmed into the nonmultiplexed serial inter-
face (NMSI) mode. This mode, which is available for one, two, or all three SCC ports, can
be selected while the other ports use one of the multiplexed interface modes (IDL, GCI, or
PCM highway).
MOTOROLA
1 GENERAL-
INTERRUPT
PURPOSE
CONTROLLER
CHANNEL
6 DMA
CHANNELS
PERIPHERAL BUS
3 SERIAL
CHANNELS
Figure 1-3. MC68302 System Design
MC68302 USER'S MANUAL
MC68302 IMP
3 TIMERS
AND
DMA
ADDITIONAL
FEATURES
68000
SYSTEM BUS
1152 BYTES
DUAL-PORT
RAM
OTHER
SERIAL
CHANNELS
General Description
RAM / ROM
OTHER
PERIPHERALS
1-5
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