Motorola MC68302 User Manual page 214

Integrated multiprotocol processor
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Communications Processor (CP)
should not write to any fields of this BD when this bit is set. The empty bit will re-
main set while the CP is currently filling the buffer with received data.
X—External Buffer
0 = The buffer associated with this BD is in internal dual-port RAM.
1 = The buffer associated with this BD is in external memory.
W—Wrap (Final BD in Table)
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
receive incoming data into the first BD in the table. Setting this bit allows the use
of fewer than eight BD to conserve internal RAM.
The user is required to set the wrap bit in one of the first eight
BDs; otherwise, errant behavior may occur.
I—Interrupt
0 = No interrupt is generated after this buffer has been used.
1 = The RX bit in the BISYNC event register will be set when this buffer has been
closed by the BISYNC controller, which can cause an interrupt.
The following status bits are written by the CP after the received data has been placed into
the associated data buffer.
C—Control Character
The last byte in the buffer is a user-defined control character.
0 = The last byte of this buffer does not contain a control character.
1 = The last byte of this buffer contains a control character.
B—BCS Received
The last bytes in the buffer contain the received BCS.
0 = This buffer does not contain the BCS.
1 = This buffer contains the BCS. A control character may also reside one byte prior to
this BCS.
Bits 9–5—Reserved for future use.
DL—DLE Follow Character Error
While in transparent mode, a DLE character was received, and the next character was not
DLE, SYNC, or a valid entry in the control characters table.
PR—Parity Error
A character with a parity error was received and is the last byte of this buffer.
4-94
NOTE
MC68302 USER'S MANUAL
MOTOROLA

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