Programming The Bisync Controllers - Motorola MC68302 User Manual

4.5.13.14 Programming the BISYNC Controllers

There are two general techniques that the software may employ to handle data received by
the BISYNC controllers. The simplest way is to allocate single-byte receive buffers, request
(in the status word in each BD) an interrupt on reception of each buffer (i.e., byte), and im-
plement the BISYNC protocol entirely in software on a byte-by-byte basis. This simple ap-
proach is flexible and may be adapted to any BISYNC implementation. The obvious penalty
is the overhead caused by interrupts on each received character.
A more efficient method is as follows. Multibyte buffers are prepared and linked to the re-
ceive buffer table. Software is used to analyze the first (two to three) bytes of the buffer to
determine what type of block is being received. When this has been determined, reception
can continue without further intervention to the user's software until a control character is
encountered. The control character signifies the end of the block, causing the software to
revert back to a byte-by-byte reception mode.
To accomplish this, the RCH bit in the BISYNC mask register should initially be set, enabling
an interrupt on every byte of data received. This allows the software to analyze the type of
block being received on a byte-by-byte basis. After analyzing the initial characters of a block,
the user should either set the receiver transparent mode (RTR) bit in the BISYNC mode reg-
ister or issue the RESET BCS CALCULATION command. For example, if DLE-STX is re-
ceived, transparent mode should be entered. By setting the appropriate bit in the BISYNC
mode register, the BISYNC controller automatically strips the leading DLE from <DLE-char-
acter> sequences. Thus, control characters are only recognized when they follow a DLE
character. The RTR bit should be cleared after a DLE-ETX is received.
Alternatively, after receiving an SOH, the RESET BCS CALCULATION command should be
issued. This command causes the SOH to be excluded from BCS accumulation and the
BCS to be reset. Note that the RBCS bit in the BISYNC mode register (used to exclude a
character from the BCS calculation) is not needed here since SYNCs and leading DLEs (in
transparent mode) are automatically excluded by the BISYNC controller.
After recognizing the type of block above, the RCH interrupt should be masked. Data recep-
tion then continues without further interruption of the M68000 core until the end of the cur-
rent block is reached. This is defined by the reception of a control character matching that
programmed in the receive control characters table.
The control characters table should be set to recognize the end of the block as follows:
After the end of text (ETX), a BCS is expected; then the buffer should be closed. Hunt mode
should be entered when line turnaround occurs. ENQ characters are used to abort transmis-
MOTOROLA
Control Characters
ETX
ITB
ETB
ENQ
Next Entry
MC68302 USER'S MANUAL
Communications Processor (CP)
E B H
0 1 1
0 1 0
0 1 1
0 0 0
1 X X
4-99